The present invention relates generally to the field of frequency dividers and, more particularly, to a frequency divider capable of high resolution, fractional division.
Programmable frequency dividers capable of integral division are well known in the art. Such dividers typically comprise a counter, e.g. a down counter, having a control input for receiving a binary control word and a clock input for receiving a high frequency clock signal. The down counter is repetitively loaded with the control word and operated at a rate set by the clock signal wherein an output pulse is developed each time a zero count is attained. Thus, in effect, the output pulses form a signal whose frequency represents the quotient of a division operation wherein the repetition rate of the clock signal represents the dividend and the value of the binary control word represents the divisor. Due to the nature of such dividers, only integral division may be achieved wherein the quotient represented by the frequency of the output signal corresponds to an integer value.
In various applications, it is desirable to effect a division operation having a relatively high degree of resolution. For example, circuits such as programmable filters, waveshapers and the like are typically operative in response to a high resolution pulse code which is often developed at the output of a conventional programmable divider. A number of circuits exemplary of the foregoing are disclosed in co-pending application, Ser. No. 835,695, filed Sept. 22, 1977, now U.S. Pat. No. 4,186,643, and entitled "Programmable Circuits for Electronic Musical Instruments". In order to achieve the high degree of resolution needed to properly operate the programmable circuits, the clock signal supplied to the divider is necessarily characterized by a relatively high repetition rate. That is, increasing the repettition rate of the clock signal supplied to the divider proportionately increases the resolution of the frequency characterizing the output signal while decreasing the repetition rate of the clock signal reduces the resolution of the frequency characterizing the output signal. Thus, theoretically, an output signal may be generated exhibiting any desired degree of resolution by simply providing a clock signal having a sufficiently high repetition rate. However, this approach to achieving high resolution rapidly become impracticable due to the frequency limitations characterizing state of the art integrated circuits. Currently available large scale integrated circuits, for example, have an operational range limited to about 4 MHz. As a result, resolution must often be sacrificed to accommodate the use of a clock signal having a repetition rate compatible with state of the art integrated circuit technology.